100G ETHERNET CORE

Apogee’s Advanced 100 Gigabit Ethernet FPGA IP Core provides high-bandwidth Ethernet, IPv4, and UDP packet processing for FPGA-based systems using AMD UltraScale+ devices.

The core uses a shared packet-processing datapath to support multiple logical Ethernet interfaces and UDP channels without replicating the complete processing pipeline.

Software configures interface MAC, VLAN and IP addresses along with UDP channel port, mapping to the AXI bus TID value.

The core supports IGMP for multicast operation which increases bandwidth efficiency with data traveling to or from multiple destinations. 

ICMP Ping support for external verification the interface is up and responding to the network. 

Address Resolution Protocol (ARP) is internal to the interfaces. The core automatically replies to external network requests. Software can perform ARP request and gratuitous 

messaging to identify MAC addresses for IP addresses on the network. 

The core interfaces directly with the AMD UltraScale+ CMAC hard IP block and provides AXI4-Stream UDP payload interfaces for connection to user-defined FPGA processing logic. Runtime configuration and control are provided through a 32-bit AXI4-Lite memory-mapped interface.