100G DIFI CORE
Multi-Channel, Independent Transmit and Receive, VITA49.2
Overview
Apogee’s 100G DIFI/IEEE-ISTO Std 4900-2021 FPGA IP core targets multi-channel, high-bandwidth digital IF applications requiring FPGA-based handling of DIFI-formatted data streams.
Designed for integration into high-throughput Software Defined Radio (SDR) and digital IF processing systems, this capability addresses the need to process signal data and associated metadata within FPGA-based architectures.
It supports over 100 Gb/s sustained processing and can operate of upstream and downstream cores, allowing designers to quickly incorporate DIFI functionality into their own FPGA architectures.
Provides AXI4-Stream payload interfaces for connection to user-defined FPGA processing logic. Runtime configuration and control are provided through a 32-bit AXI4-Lite memory-mapped interface.
Key Features
- Over 100 Gb/s processing capability: Sustained DIFI processing in a standalone FPGA IP solution
- Bidirectional packet processing: Receive-side header parsing and payload extraction, with transmit-side DIFI header generation and payload encapsulation.
- Configurable multi-channel routing: A 16-channel default configuration with individual channel enables and routing based on Transfer ID, Packet Type, and Stream ID where present.
- Timestamp and sequence preservation: Received integer and fractional timestamps, along with packet sequence numbers, remain available to downstream logic through AXI4-Stream TUSER.
- DIFI context-packet handling: Capture received context packets for software readback and transmit software-supplied context packets through the AXI4-Lite interface.
- Per-channel buffering: Individual FIFOs support receive-stream demultiplexing and transmit-stream multiplexing.
- AXI4-Stream data interfaces: Default 512-bit network-facing and 32-bit processing-facing data paths.
- Software-accessible control and monitoring: AXI4-Lite configuration registers and 64-bit per-channel receive and transmit packet counters with individual reset capability.
- Modular FPGA implementation: Separate RX Processor, RX Demux, TX Mux, and TX Processor modules, with channel-count customization and integration through the Vivado IP Catalog.
